1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having an improved data readout circuit.
2. Description of the Related Art
Generally, in the nonvolatile semiconductor memory device such as an EPROM, the potential of a bit line to which a selected memory cell is connected is compared with a reference potential created using a dummy cell and data of "1" or "0" is read out based on the comparison result.
The bit line potential varies according to data stored in the memory cell. That is, when data "0" is stored in the memory cell, the bit line potential is set and kept at a preset high potential level which has been precharged by means of a load circuit. In contrast, when data "1" is stored, the bit line is discharged via the cell transistor and the bit line potential is set to a low potential level. The reference potential is set at an intermediate potential level between the high and low potential levels of the bit line potential. Therefore, the result of comparison between the bit line potential and the reference potential will become different according to data stored in the memory cell so that data "0" or "1" can be read out.
However, in order to read out data "1" from the memory device of the above-described data readout system, the bit line potential must be lowered from the high potential level to the low potential level only through the discharging operation via the cell transistor. As a result, it takes a long time to read out data.
A nonvolatile semiconductor memory device shown in FIG. 1 is proposed to enhance the data readout speed. The memory device is disclosed in the document ("A Programmable 1Mb CMOS EPROM" ISSCC Digest of Technical Papers, pp. 176 to 177, 1985). The memory device is constructed such that bit line BL is precharged to an intermediate potential for a preset period of time by means of intermediate potential generating circuit 10 and then the potential of bit line BL is compared with that of dummy bit line DBL by means of sense amplifier 20.
In this case, as shown in FIG. 1, potential separation transfer gate transistors Q1 and Q2 are respectively connected between bit line BL and sense amplifier 20 and between dummy bit line DBL and sense amplifier 20. Therefore, sense amplifier 20 actually compares sense input signal Sin of node N1 supplied from a main circuit with reference potential Vref of node N2 on the dummy cell side.
Further, in the EPROM, address transition detecting circuit (ATD) 10a is used for generating pre-charging signal PC. In other words, when the transition of the memory address designated by the address signal is detected by means of ATD 10a, a pulse signal of a preset pulse width is supplied via delay circuit 10b and NAND gate 10c and used as pre-charging signal PC.
If the potential of bit line BL is set to the intermediate potential, it is only necessary to lower the bit line potential from the intermediate potential level to the low potential level when data "1" is read out. As a result, the data readout speed becomes high in comparison with the case where the bit line potential is lowered from the high potential level to the low potential level.
However, in the EPROM, as shown in FIGS. 2 and 3, sense amplifier input signal Sin will sway or fluctuate in a short period after pre-charging signal PC is reset, and it takes some time until data is determined.
FIG. 2 is a waveform diagram showing the readout operation in a case where data "1" is stored in memory cell MC. Theoretically, sense input signal Sin will start to be lowered at time t0 at which pre-charging signal PC has been changed from "1" to "0". Actually, however, as shown in FIG. 2, sense signal Sin fluctuates in period T1 from t0 to t1 and the potential level thereof is first raised and then lowered. Therefore, the readout data cannot be determined until period T1 from rising time t0 of pre-charging signal PC has elapsed.
Further, as shown in FIG. 3, in a case where data "0" is stored in selected memory cell MC, sense signal Sin will fluctuate in period T2 from rising time t0 of pre-charging signal PC to time t2.
The fluctuation in sense signal Sin is caused by setting of the potential of bit line BL to the intermediate potential level. During the fluctuation in the potential, it is practically impossible to correctly read out data, and as a result, the data readout speed is lowered.